PULP Platform @pulp_platform
A joint effort of @ETH_en, University of Bologna @Unibo + partners for Parallel Ultra-Low Power computing. Boldly designing open hardware since '13. pulp-platform.org Joined February 2016-
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A new addition to our team! Here is Paolo who works on MemPool, a scalable RISC-V many-core system, with interests in shared-memory architectures, on-chip communication, and SW for DSP workloads. Welcome to PULP!
Here is our paper "CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees". Fabricated in GF 22 FDX. See arxiv.org/pdf/2606.02358
We present "O-POPE: High-Frequency Pipelined Outer Product based GEMM acceleration with minimal buffering overhead" achieved by repurposing FPU pipeline registers as buffers: arxiv.org/pdf/2606.02333 @Ang__93
The 22nd edition of the @hipeac summer school ACACES 2026 will take place in Fiuggi 12-18 July hipeac.net/acaces/2026/#/! Our Angelo @Ang__93 will be teaching "Hardware/Software Co-design of Energy Efficient RISC-V Edge AI Platforms". See more: hipeac.net/acaces/2026/#/
Today, Charlie The Bear would like to introduce our new team member Marco. Marco works on fault-tolerant GEMM design for satellite RISC-V clusters executing SLMs, and its physical implementation and reliability assessment. Welcome to the team!
We are getting ready for the #RISCVSummitEurope Bologna! Black or white? What do you say?
Time to celebrate! Our colleague Tim @fischetim just defended his PhD thesis "Scalable Interconnects for Integrated Accelerators". Warmest congratulations to you from Charlie The Bear and the entire PULP team.
We were delighted to welcome Martin Poviser from OpenRoad/PrecisionInno in our lab. Below, you can see Frank, Charlie and Yukio helping Martin choose the best PULP sticker for his laptop. Thank you, Alan Mishchenko, for taking the pictures!
Can't wait to show a heterogeneous, all RISC-V "AI factory" machine... stay tuned... working with @tenstorrent @AxeleraAI and more!
RISC-V compute nodes are closing the gap with their competitors in the HPC segment! Check out our collaborative paper "Monte Cimone v3: Where RISC-V Stands in High-Performance Computing" arxiv.org/pdf/2605.22831
RISC-V compute nodes are closing the gap with their competitors in the HPC segment! Check out our collaborative paper "Monte Cimone v3: Where RISC-V Stands in High-Performance Computing" arxiv.org/pdf/2605.22831
#MLSys2026 just took place in Bellevue & we were there with Luca presenting "A Lightweight High-Throughput Collective-Capable NoC for Large-Scale ML Accelerators". See arxiv.org/abs/2603.26438 github.com/pulp-platform/… pulp-platform.org/docs/mlsys2026… pulp-platform.org/docs/mlsys2026… @lucacolagrande3
We are incredibly proud of all our team members who took part in this year's edition of the SOLA Stafette Zurich. We ranked 136th in over 1000 teams. An achievement that we triumphantly celebrated: trackmaxx.ch/results/?race=… @CristiCioflan
Amirhossein's talk "Threads or Vectors? Evaluating SPMD and Vector Accelerators for Resource Constrained RISC-V Architectures" presented at #CF2026 in Catania is now online, as well. Find it here: pulp-platform.org/docs/cf2026/Am…
The slides from Yichao's @yichao_zh #CF2026 Catania talk "A 8.4 TFLOPS@16b/4.3W General-Purpose Programmable Accelerated Cluster for AI-Native RAN" are now online, as well. Check them out: pulp-platform.org/docs/cf2026/Te…
Maoyuan, too, presented her work "Not All Faults Are Equal: Transient-Fault Sensitivity Characterization of an Open-Source RISC-V Vector Cluster" at #CF2026 in Catania. Find her slides on our website: pulp-platform.org/docs/cf2026/CF…
And here is Kai, our new team member. Kai works on developing next-generation processing platforms for space. Welcome to the PULP team and hugs from Charlie The Bear!
Computing Frontiers are currently underway at the Museo Diocesano di Catania and we are there with Yichao @yichao_zh who will present "A 8.4 TFLOPS@16b/4.3W General Purpose Programmable Accelerated Cluster for AI-Native RAN" at 14:25 local time today. See computingfrontiers.org/2026/program.h…
Today we would like to introduce PULP's new team member Cong who works on DNN deployment flows and simulation platform extensions for heterogeneous RISC-V SoCs, targeting large-scale mesh accelerators via Deeploy and GVSoC. Welcome to the team!
We introduce Multi-Resolution Rescored ByteTrack "MR2-ByteTrack: CNN and Transformer-based Video Object Detection for AI-augmented Embedded Vision Sensor Nodes" which reduces computational cost by alternating between full- and low-resolution inference. See arxiv.org/pdf/2605.15423
Our paper "EAGLE: A Flexible Heterogeneous Analog Compute-In-Memory Architecture With RISC-V Programmable Multi-Core Accelerators," is now available in the "Early Access" on IEEE Xplore: ieeexplore.ieee.org/document/11517…
Matthew Venn @matthewvenn
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Olof Kindgren @OlofKindgren
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Enjoy Digital @enjoy_digital
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Enjoy Digital @enjoy_digital
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Jon Masters 🏴�... @jonmasters
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Hans Baier @hansfbaie... @hansfbaier
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9K Followers 751 Following mostly about open source FPGA tools and chip design tools
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