Zip CPU @zipcpu

FPGA design engineer and blogger, placing particular emphasis on test and formal verification zipcpu.com Gisselquist Technology, LLC, Joined January 2017

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Zip CPU @zipcpu

20 hours ago

Turns out, it had passed a minimal cover check -- I had just forgotten that when posting. 🙄

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Zip CPU @zipcpu

a day ago

Increasing the AXI bus size isn't nearly as difficult as I feared. Now all I need a project to test this on ... You can see my first attempts here: github.com/ZipCPU/wb2axip…

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Zip CPU @zipcpu

a day ago

General Washington has some good advice for our times.

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Zip CPU @zipcpu

2 days ago

BIST -- that wonderful "Built-In Self-Testing" capability everyone wants. It sounds easy. It's just a basic FSM, coupled with bidirectional IOs, right? Not so fast.

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Zip CPU @zipcpu

2 days ago

@bradipao Exactly, but ... you can't use that bit when referencing the memory.

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You build it, formally verify it, place it on the shelf, use it for years, and just change on parameter option--adjusting things to make timing pass. Suddenly, the design that worked a day ago suddenly stops working and the "bug" is in something that was previously verified

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Zip CPU @zipcpu

2 days ago

rd_addr has one more bit than w_rd_addr. There are only 0x40 memory locations (in this example). If you want to use all 0x40 memory locations, you need an extra address bit. However, if you try to read from location 0x40, using this extra address bit, the simulator doesn't trim the address but rather tries to read off the end of memory, and so it returns all x's from a memory location that doesn't exist and that you never intended to read from.

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Zip CPU @zipcpu

6 days ago

@meteorvanilla QSPI uses this pin as a data pin. It's a HOLD# pin while in SPI, then converts to a data pin in QSPI. Yes, you can get 2x the throughput in QSPI over Dual SPI, and 4x the throughput over regular SPI.

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Zip CPU @zipcpu

a week ago

It's always the little things that will get you. Here's a bug from last week, that I finally figured out today.

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Zip CPU @zipcpu

6 days ago

From a briefing today on clock/data recovery in digital (FPGA) logic, here's the key statistical property required to make clock recovery happen. This assumes a sufficiently pseudorandom data stream.

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Zip CPU @zipcpu

6 days ago

@sunaabhtrivedi The file in question HAD default_nettype set to none. Vivado only generated a warning, not an error like it should have.

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Zip CPU @zipcpu

7 days ago

Today I learned that Vivado's warnings about undeclared signals shouldn't be ignored. Vivado created signals to replace those I used prior to their declarations, and then created *NEW* ones when it got to the declaration! That should be an *ERROR*, not a warning.

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Sk Akram @akramcodez

3 months ago

this is the biggest lie in the universe

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Zip CPU @zipcpu

7 days ago

Lesson learned: If you don't need an IDELAYCTRL resource, don't declare it.

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Zip CPU @zipcpu

7 days ago

Bug #2 of the day: Apparently Vivado ignores the IDELAYCTRL group name if both IDELAYCTRL groups aren't used. I had one IDELAYCTRL for HDMI (at 300MHz) which had no signals attached, and another in use for the DDR3 (at 200MHz), and Vivado got the two confused.

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Zip CPU @zipcpu

a week ago

Sadly, the error could be seen in the first trace. Beware of that HOLD# pin when working with SPI based flash devices. You can't ignore it. It must be set properly if you want MISO and MOSI to work properly.

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Zip CPU @zipcpu

a week ago

Everything looked good and clean (to me), the flash just never responded. I even asked the board designer to come to the lab to help make sure the pins toggled. I just couldn't see any errors in the traces.

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Zip CPU @zipcpu

a week ago

Today's bug: Using an outdated schematic. 9 pins were mis-routed. This killed some serious capabilities. This was an expensive error, as well, since it required an hour of time from multiple engineers to find the bug. Oops.

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Zip CPU @zipcpu

a week ago

This needs some sort of theme music ... jeopardy, or whistling?

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Zip CPU @zipcpu

a week ago

And performance? WRITE cost => 1 extra beat of latency READ cost => 2 extra beats of latency There's also the opportunity cost for under-utilizing the bus like this.

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Zip CPU @zipcpu

a week ago

... and now for the READ side.

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Zip CPU @zipcpu

a week ago

It's always fun getting to the cover() portion of the proof, where you can determine just how deep the proof needs to be, but more importantly you can see and share how it works. Here's the WRITE side.

Zip CPU @zipcpu

a week ago

It's a holiday! Today's project will have nothing to do with memory controllers. How about an AXI bus resizing tool? Something to go from a smaller bus to a bigger one?